欢迎访问ic37.com |
会员登录 免费注册
发布采购

EP1S20F672C7N 参数 Datasheet PDF下载

EP1S20F672C7N图片预览
型号: EP1S20F672C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 2132 CLBs, 18460-Cell, CMOS, PBGA672, 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, BGA-672]
分类和应用:
文件页数/大小: 292 页 / 1528 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EP1S20F672C7N的Datasheet PDF文件第83页浏览型号EP1S20F672C7N的Datasheet PDF文件第84页浏览型号EP1S20F672C7N的Datasheet PDF文件第85页浏览型号EP1S20F672C7N的Datasheet PDF文件第86页浏览型号EP1S20F672C7N的Datasheet PDF文件第88页浏览型号EP1S20F672C7N的Datasheet PDF文件第89页浏览型号EP1S20F672C7N的Datasheet PDF文件第90页浏览型号EP1S20F672C7N的Datasheet PDF文件第91页  
Stratix Architecture  
Adder/Subtractor/Accumulator  
The adder/subtractor/accumulator is the first level of the adder/output  
block and can be used as an accumulator or as an adder/subtractor.  
Adder/Subtractor  
Each adder/subtractor/accumulator block can perform addition or  
subtraction using the addnsubindependent control signal for each first-  
level adder in 18 × 18-bit mode. There are two addnsub[1..0]signals  
available in a DSP block for any configuration. For 9 × 9-bit mode, one  
addnsub[1..0]signal controls the top two one-level adders and  
another addnsub[1..0]signal controls the bottom two one-level  
adders. A high addnsubsignal indicates addition, and a low signal  
indicates subtraction. The addnsubcontrol signal can be unregistered or  
registered once or twice when feeding the adder blocks to match data  
path pipelines.  
The signaand signbsignals serve the same function as the multiplier  
block signaand signbsignals. The only difference is that these signals  
can be registered up to two times. These signals are tied to the same  
signaand signbsignals from the multiplier and must be connected to  
the same clocks and control signals.  
Accumulator  
When configured for accumulation, the adder/output block output feeds  
back to the accumulator as shown in Figure 2–34. The  
accum_sload[1..0]signal synchronously loads the multiplier result  
to the accumulator output. This signal can be unregistered or registered  
once or twice. Additionally, the overflowsignal indicates the  
accumulator has overflowed or underflowed in accumulation mode. This  
signal is always registered and must be externally latched in LEs if the  
design requires a latched overflowsignal.  
Summation  
The output of the adder/subtractor/accumulator block feeds to an  
optional summation block. This block sums the outputs of the DSP block  
multipliers. In 9 × 9-bit mode, there are two summation blocks providing  
the sums of two sets of four 9 × 9-bit multipliers. In 18 × 18-bit mode, there  
is one summation providing the sum of one set of four 18 × 18-bit  
multipliers.  
Altera Corporation  
July 2005  
2–63  
Stratix Device Handbook, Volume 1  
 
 
 
 复制成功!