Digital Signal Processing Block
Figure 2–34. Adder/Output Blocks Note (1)
Accumulator Feedback
accum_sload0 (2)
Result A
overflow0
Adder/
Subtractor/
addnsub1 (2)
Accumulator1
Output Selection
Multiplexer
Result B
signa (2)
Summation
Output
Register Block
signb (2)
Result C
Adder/
Subtractor/
Accumulator2
addnsub3 (2)
overflow1
Result D
accum_sload1 (2)
Accumulator Feedback
Notes to Figure 2–34:
(1) Adder/output block shown in Figure 2–34 is in 18 × 18-bit mode. In 9 × 9-bit mode, there are four adder/subtractor
blocks and two summation blocks.
(2) These signals are either not registered, registered once, or registered twice to match the data path pipeline.
2–62
Altera Corporation
July 2005
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
