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EP1S20F672C7N 参数 Datasheet PDF下载

EP1S20F672C7N图片预览
型号: EP1S20F672C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 2132 CLBs, 18460-Cell, CMOS, PBGA672, 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, BGA-672]
分类和应用:
文件页数/大小: 292 页 / 1528 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix Architecture  
Figure 2–35. Simple Multiplier Mode  
signa (1)  
signb (1)  
aclr  
clock  
ena  
shiftin A  
shiftin B  
D
Q
Data A  
Data B  
Data Out  
D
Q
ENA  
D
Q
ENA  
ENA  
CLRN  
CLRN  
CLRN  
D
Q
ENA  
CLRN  
shiftout B shiftout A  
Note to Figure 2–35:  
(1) These signals are not registered or registered once to match the data path pipeline.  
DSP blocks can also implement one 36 × 36-bit multiplier in multiplier  
mode. DSP blocks use four 18 × 18-bit multipliers combined with  
dedicated adder and internal shift circuitry to achieve 36-bit  
multiplication. The input shift register feature is not available for the  
36 × 36-bit multiplier. In 36 × 36-bit mode, the device can use the register  
that is normally a multiplier-result-output register as a pipeline stage for  
the 36 × 36-bit multiplier. Figure 2–36 shows the 36 × 36-bit multiply  
mode.  
Altera Corporation  
July 2005  
2–65  
Stratix Device Handbook, Volume 1