Timing Model
Tables 4–105 through 4–108 show the output adder delays associated
with column and row I/O pins for both fast and slow slew rates. If an I/O
standard is selected other than 3.3-V LVTTL 4mA or LVCMOS 2 mA with
a fast slew rate, add the selected delay to the external tOUTCO, tOUTCOPLL
tXZ, tZX, tXZPLL, and tZXPLL I/O parameters shown in Table 4–55 on
page 4–36 through Table 4–96 on page 4–56.
,
Table 4–105. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 1 of 2)
-5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
Max
LVCMOS
2 mA
4 mA
1,895
956
189
0
1,990
1,004
198
1,990
1,004
198
0
1,990
1,004
198
0
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
8 mA
12 mA
24 mA
4 mA
0
–157
1,895
1,347
636
561
0
–165
1,990
1,414
668
–165
1,990
1,414
668
589
0
–165
1,990
1,414
668
589
0
3.3-V LVTTL
2.5-V LVTTL
8 mA
12 mA
16 mA
24 mA
2 mA
589
0
2,517
834
504
194
1,304
960
960
6,680
3,275
1,589
16
2,643
875
2,643
875
529
203
1,369
1,008
1,008
7,014
3,439
1,668
17
2,643
875
529
203
1,369
1,008
1,008
7,014
3,439
1,668
17
8 mA
12 mA
16 mA
2 mA
529
203
1.8-V LVTTL
1.5-V LVTTL
1,369
1,008
1,008
7,014
3,439
1,668
17
8 mA
12 mA
2 mA
4 mA
8 mA
GTL
GTL+
9
9
9
9
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
50
52
52
52
50
52
52
52
50
52
52
52
50
52
52
52
AGP 2×
1,895
1,990
1,990
1,990
4–68
Altera Corporation
January 2006
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
