DC & Switching Characteristics
Table 4–104. Stratix I/O Standard Row Pin Input Delay Adders
-5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
Max
LVCMOS
0
0
0
0
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
GTL+
0
0
0
0
21
22
25
29
181
300
–152
–168
–193
–193
–262
–262
–105
0
190
315
–160
–177
–203
–203
–276
–276
–111
0
218
362
–184
–203
–234
–234
–317
–317
–127
0
257
426
–216
–239
–275
–275
–373
–373
–150
0
CTT
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.8-V HSTL Class I
LVDS
–151
–126
–149
–149
–65
77
–159
–133
–157
–157
–69
–81
–183
–153
–180
–180
–79
–93
–215
–179
–212
–212
–93
LVPECL
3.3-V PCML
HyperTransport
–110
Altera Corporation
January 2006
4–67
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
