Timing Model
Table 4–102 shows the reporting methodology used by the Quartus II
software for minimum timing information for output pins.
Table 4–102. Reporting Methodology For Minimum Timing For Single-Ended Output Pins (Part 1 of 2)
Notes (1), (2), (3)
Measurement
Loading and Termination
Point
I/O Standard
RUP
RDN
RS
RT
VCCIO
(V)
CL
VTT
(V)
VMEAS
(pF)
Ω
Ω
Ω
Ω
3.3-V LVTTL
–
–
–
–
0
0
–
–
3.600
2.630
1.950
1.600
3.600
2.630
1.950
1.600
3.600
2.630
3.600
2.630
3.600
3.600
2.630
2.630
1.950
1.950
1.600
1.600
1.950
1.950
3.600
3.600
3.600
3.600
3.600
2.630
1.950
1.600
3.600
2.630
1.950
1.600
1.260
1.260
1.650
1.650
1.750
1.750
1.390
1.390
1.040
1.040
0.800
0.800
0.900
0.900
1.950
1.950
3.600
3.600
10
10
10
10
10
10
10
10
30
30
30
30
30
30
30
30
30
30
20
20
20
20
10
10
10
10
1.800
1.200
2.5-V LVTTL
1.8-V LVTTL
–
–
0
–
0.880
1.5-V LVTTL
–
–
0
–
0.750
3.3-V LVCMOS
2.5-V LVCMOS
1.8-V LVCMOS
1.5-V LVCMOS
3.3-V GTL
–
–
0
–
1.800
–
–
0
–
1.200
–
–
0
–
0.880
–
–
0
–
0.750
–
–
0
25
25
25
25
25
50
25
50
25
50
25
50
25
50
–
0.860
2.5-V GTL
–
–
0
0.860
3.3-V GTL+
–
–
0
1.120
2.5-V GTL+
–
–
0
1.120
3.3-V SSTL-3 Class II
3.3-V SSTL-3 Class I
2.5-V SSTL-2 Class II
2.5-V SSTL-2 Class I
1.8-V SSTL-18 Class II
1.8-V SSTL-18 Class I
1.5-V HSTL Class II
1.5-V HSTL Class I
1.8-V HSTL Class II
1.8-V HSTL Class I
3.3-V PCI (4)
–
–
25
25
25
25
25
25
0
1.750
–
–
1.750
–
–
1.390
–
–
1.390
–
–
1.040
–
–
1.040
–
–
0.900
–
–
0
0.900
–
–
0
1.000
–
–
0
1.000
–/25
–/25
–/25
–/25
25/–
25/–
25/–
25/–
0
1.026/2.214
1.026/2.214
1.026/2.214
1.026/2.214
0
–
3.3-V PCI-X 1.0 (4)
3.3-V Compact PCI (4)
3.3-V AGP 1× (4)
0
–
0
–
4–64
Altera Corporation
January 2006
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
