DC & Switching Characteristics
Table 4–101. Reporting Methodology For Maximum Timing For Single-Ended Output Pins (Part 2 of 2)
Notes (1), (2), (3)
Measurement
Loading and Termination
Point
I/O Standard
RUP
RDN
RS
RT
VCCIO
(V)
CL
VTT
(V)
VMEAS
(pF)
Ω
Ω
Ω
Ω
3.3-V SSTL-3 Class I
2.5-V SSTL-2 Class II
2.5-V SSTL-2 Class I
1.8-V SSTL-18 Class II
1.8-V SSTL-18 Class I
1.5-V HSTL Class II
1.5-V HSTL Class I
1.8-V HSTL Class II
1.8-V HSTL Class I
3.3-V PCI (4)
–
–
–
–
25
25
25
25
25
0
50
25
50
25
50
25
50
25
50
–
2.950
2.370
2.370
1.650
1.650
1.400
1.400
1.650
1.650
2.950
2.950
2.950
2.950
2.050
1.250
1.110
1.110
0.760
0.760
0.700
0.700
0.700
0.700
2.950
2.950
2.950
2.950
1.350
30
30
30
30
30
20
20
20
20
10
10
10
10
30
1.250
1.110
–
–
1.110
–
–
0.760
–
–
0.760
–
–
0.680
–
–
0
0.680
–
–
0
0.880
–
–
0
0.880
–/25
–/25
–/25
–/25
–
25/–
25/–
25/–
25/–
–
0
0.841/1.814
0.841/1.814
0.841/1.814
0.841/1.814
1.350
0
–
3.3-V PCI-X 1.0 (4)
3.3-V Compact PCI (4)
3.3-V AGP 1X (4)
0
–
0
–
3.3-V CTT
25
50
Notes to Table 4–101:
(1) Input measurement point at internal node is 0.5 × VCCINT
.
(2) Output measuring point for data is VMEAS
.
(3) Input stimulus edge rate is 0 to VCCINT in 0.5 ns (internal signal) from the driver preceding the IO buffer.
(4) The first value is for output rising edge and the second value is for output falling edge. The hyphen (-) indicates
infinite resistance or disconnection.
Altera Corporation
January 2006
4–63
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
