Timing Model
Figure 4–7. Output Delay Timing Reporting Setup Modeled by Quartus II
VCCIO
Single-Ended Outputs
VCCIO
VTT
RUP
RS
RT
Output
Buffer
OUTPUT
VMEAS
CL
RDN
GND
GND
GND
Notes to Figure 4–7:
(1) Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
(2) VCCINT is 1.42-V unless otherwise specified.
Table 4–101. Reporting Methodology For Maximum Timing For Single-Ended Output Pins (Part 1 of 2)
Notes (1), (2), (3)
Measurement
Loading and Termination
Point
I/O Standard
RUP
RDN
RS
RT
VCCIO
(V)
CL
VTT
(V)
VMEAS
(pF)
Ω
Ω
Ω
Ω
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
3.3-V LVCMOS
2.5-V LVCMOS
1.8-V LVCMOS
1.5-V LVCMOS
3.3-V GTL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
–
–
2.950
2.370
1.650
1.400
2.950
2.370
1.650
1.400
2.950
2.370
2.950
2.370
2.950
2.95
2.37
1.65
1.40
2.95
2.37
1.65
1.40
1.14
1.14
1.35
1.35
1.25
10
10
10
10
10
10
10
10
30
30
30
30
30
1.500
1.200
0.880
0.750
1.500
1.200
0.880
0.750
0.740
0.740
0.880
0.880
1.250
0
–
0
–
0
–
0
–
0
–
0
–
0
25
25
25
25
25
2.5-V GTL
0
3.3-V GTL+
0
2.5-V GTL+
0
3.3-V SSTL-3 Class II
25
4–62
Altera Corporation
January 2006
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
