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EP1S20F672C7N 参数 Datasheet PDF下载

EP1S20F672C7N图片预览
型号: EP1S20F672C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 2132 CLBs, 18460-Cell, CMOS, PBGA672, 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, BGA-672]
分类和应用:
文件页数/大小: 292 页 / 1528 K
品牌: ALTERA [ ALTERA CORPORATION ]
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DC & Switching Characteristics  
Table 4–97. Output Pin Timing Skew Definitions (Part 2 of 2)  
Symbol  
Definition  
tLR_HIO  
tTB_VIO  
tOVERALL  
Across all HIO banks (1, 2, 5, 6); across four similar  
type I/O banks  
Across all VIO banks (3, 4, 7, 8); across four similar  
type I/O banks  
Output timing skew for all I/O pins on the device.  
Notes to Table 4–97:  
(1) See Figure 4–5 on page 4–57.  
(2) See Figure 4–6 on page 4–58.  
Table 4–98 shows the I/O skews when using the same global or regional  
clock to feed IOE registers in I/O banks around each device. These values  
can be used for calculating the timing budget on the output (write) side  
of a memory interface. These values already factor in the package skew.  
Table 4–98. Output Skew for Stratix by Device Density  
Skew (ps) (1)  
Symbol  
EP1S10 to EP1S30  
EP1S40  
290  
EP1S60 & EP1S80  
tSB_HIO  
tSB_VIO  
tSS_HIO  
tSS_VIO  
tLR_HIO  
tTB_VIO  
tOVERALL  
90  
500  
500  
600  
630  
600  
670  
880  
160  
90  
290  
460  
180  
150  
190  
430  
520  
490  
580  
630  
Note to Table 4–98:  
(1) The skew numbers in Table 4–98 account for worst case package skews.  
Altera Corporation  
January 2006  
4–59  
Stratix Device Handbook, Volume 1