Timing Model
Figure 4–6 shows the case where four IOE registers are located in two
different I/O banks.
Figure 4–6. I/O Skew Across Two I/O Banks
I/O Bank
I/O Pin A
I/O Pin B
Common Source of GCLK
I/O Pin C
I/O Pin D
I/O Bank
I/O Pin Skew across
two Banks
I/O Pin A
I/O Pin B
I/O Pin C
I/O Pin D
Table 4–97 defines the timing parameters used to define the timing for
horizontal I/O pins (side banks 1, 2, 5, 6) and vertical I/O pins (top and
bottom banks 3, 4, 7, 8). The timing parameters define the skew within an
I/O bank, across two neighboring I/O banks on the same side of the
device, across all horizontal I/O banks, across all vertical I/O banks, and
the skew for the overall device.
Table 4–97. Output Pin Timing Skew Definitions (Part 1 of 2)
Symbol
Definition
tSB_HIO
tSB_VIO
tSS_HIO
Row I/O (HIO) within one I/O bank (1)
Column I/O (VIO) within one I/O bank (1)
Row I/O (HIO) same side of the device, across two
banks (2)
tSS_VIO
Column I/O (VIO) same side of the device, across two
banks (2)
4–58
Stratix Device Handbook, Volume 1
Altera Corporation
January 2006
ALTERA [ ALTERA CORPORATION ]
