DC & Switching Characteristics
Figure 4–3 shows the TriMatrix memory waveforms for the M512, M4K,
and M-RAM timing parameters shown in Tables 4–40 through 4–42.
Figure 4–3. Dual-Port RAM Timing Microparameter Waveform
wrclock
tWEREH
tWERESU
wren
tWADDRH
tWADDRSU
an-1
an
a0
a1
a2
a3
a4
a5
wraddress
data-in
a6
tDATAH
din-1
din4
din5
din6
din
tDATASU
rdclock
tWEREH
tWERESU
rden
tRC
rdaddress
bn
b1
b2
b3
b0
tDATACO1
doutn-1
doutn
dout0
reg_data-out
doutn-2
tDATACO2
doutn
doutn-1
dout0
unreg_data-out
Internal timing parameters are specified on a speed grade basis
independent of device density. Tables 4–44 through 4–50 show the
internal timing microparameters for LEs, IOEs, TriMatrix memory
structures, DSP blocks, and MultiTrack interconnects.
Table 4–43. Routing Delay Internal Timing Microparameter
Descriptions (Part 1 of 2)
Symbol
Parameter
tR4
Delay for an R4 line with average loading; covers a distance of four
LAB columns.
tR8
Delay for an R8 line with average loading; covers a distance of eight
LAB columns.
tR24
Delay for an R24 line with average loading; covers a distance of 24
LAB columns.
Altera Corporation
January 2006
4–27
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
