Timing Model
Table 4–42. M-RAM Block Internal Timing Microparameter
Descriptions (Part 2 of 2)
Symbol
tMRAMDATABH
tMRAMADDRBSU
tMRAMADDRBH
tMRAMDATACO1
tMRAMDATACO2
tMRAMCLKHL
Parameter
B port hold time after clock
B port address setup time before clock
B port address hold time after clock
Clock-to-output delay when using output registers
Clock-to-output delay without output registers
Register minimum clock high or low time. This is a limit on
the min time for the clock on the registers in these blocks.
The actual performance is dependent upon the internal
point-to-point delays in the blocks and may give slower
performance as shown in Table 4–36 on page 4–20 and as
reported by the timing analyzer in the Quartus II software.
tMRAMCLR
Minimum clear pulse width.
4–26
Stratix Device Handbook, Volume 1
Altera Corporation
January 2006
ALTERA [ ALTERA CORPORATION ]
