DC & Switching Characteristics
Table 4–41. M4K Block Internal Timing Microparameter Descriptions (Part
2 of 2)
Symbol
Parameter
tM4KDATAAH
A port data hold time after clock
tM4KADDRASU
tM4KADDRAH
tM4KDATABSU
tM4KDATABH
tM4KADDRBSU
tM4KADDRBH
tM4KDATACO1
tM4KDATACO2
tM4KCLKHL
A port address setup time before clock
A port address hold time after clock
B port data setup time before clock
B port data hold time after clock
B port address setup time before clock
B port address hold time after clock
Clock-to-output delay when using output registers
Clock-to-output delay without output registers
Register minimum clock high or low time. This is a limit on
the min time for the clock on the registers in these blocks.
The actual performance is dependent upon the internal
point-to-point delays in the blocks and may give slower
performance as shown inTable 4–36 on page 4–20 and as
reported by the timing analyzer in the Quartus II software.
tM4KCLR
Minimum clear pulse width
Table 4–42. M-RAM Block Internal Timing Microparameter
Descriptions (Part 1 of 2)
Symbol
Parameter
tMRAMRC
Synchronous read cycle time
tMRAMWC
Synchronous write cycle time
tMRAMWERESU
tMRAMWEREH
tMRAMCLKENSU
tMRAMCLKENH
tMRAMBESU
Write or read enable setup time before clock
Write or read enable hold time after clock
Clock enable setup time before clock
Clock enable hold time after clock
Byte enable setup time before clock
Byte enable hold time after clock
A port data setup time before clock
A port data hold time after clock
tMRAMBEH
tMRAMDATAASU
tMRAMDATAAH
tMRAMADDRASU
tMRAMADDRAH
tMRAMDATABSU
A port address setup time before clock
A port address hold time after clock
B port setup time before clock
Altera Corporation
January 2006
4–25
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
