Timing Model
Table 4–40. M512 Block Internal Timing Microparameter Descriptions
Symbol Parameter
tM512RC
Synchronous read cycle time
tM512WC
Synchronous write cycle time
tM512WERESU
tM512WEREH
tM512CLKENSU
tM512CLKENH
tM512DATASU
tM512DATAH
Write or read enable setup time before clock
Write or read enable hold time after clock
Clock enable setup time before clock
Clock enable hold time after clock
Data setup time before clock
Data hold time after clock
tM512WADDRSU
tM512WADDRH
tM512RADDRSU
tM512RADDRH
tM512DATACO1
tM512DATACO2
tM512CLKHL
Write address setup time before clock
Write address hold time after clock
Read address setup time before clock
Read address hold time after clock
Clock-to-output delay when using output registers
Clock-to-output delay without output registers
Register minimum clock high or low time. This is a limit on
the min time for the clock on the registers in these blocks.
The actual performance is dependent upon the internal
point-to-point delays in the blocks and may give slower
performance as shown in Table 4–36 on page 4–20 and as
reported by the timing analyzer in the Quartus II software.
tM512CLR
Minimum clear pulse width
Table 4–41. M4K Block Internal Timing Microparameter Descriptions (Part
1 of 2)
Symbol
Parameter
tM4KRC
Synchronous read cycle time
tM4KWC
Synchronous write cycle time
tM4KWERESU
tM4KWEREH
tM4KCLKENSU
tM4KCLKENH
tM4KBESU
Write or read enable setup time before clock
Write or read enable hold time after clock
Clock enable setup time before clock
Clock enable hold time after clock
Byte enable setup time before clock
Byte enable hold time after clock
tM4KBEH
tM4KDATAASU
A port data setup time before clock
4–24
Stratix Device Handbook, Volume 1
Altera Corporation
January 2006
ALTERA [ ALTERA CORPORATION ]
