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EP1S20F672C7N 参数 Datasheet PDF下载

EP1S20F672C7N图片预览
型号: EP1S20F672C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 2132 CLBs, 18460-Cell, CMOS, PBGA672, 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, BGA-672]
分类和应用:
文件页数/大小: 292 页 / 1528 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Configuration & Testing  
The Stratix device instruction register length is 10 bits and the USERCODE  
register length is 32 bits. Tables 3–2 and 3–3 show the boundary-scan  
register length and device IDCODE information for Stratix devices.  
Table 3–2. Stratix Boundary-Scan Register Length  
Device  
Boundary-Scan Register Length  
EP1S10  
EP1S20  
EP1S25  
EP1S30  
EP1S40  
EP1S60  
EP1S80  
1,317  
1,797  
2,157  
2,253  
2,529  
3,129  
3,777  
Table 3–3. 32-Bit Stratix Device IDCODE  
IDCODE (32 Bits) (1)  
Device  
Manufacturer Identity  
Version (4 Bits)  
Part Number (16 Bits)  
LSB (1 Bit) (2)  
(11 Bits)  
EP1S10  
EP1S20  
EP1S25  
EP1S30  
EP1S40  
EP1S60  
EP1S80  
0000  
0000  
0000  
0000  
0000  
0000  
0000  
0010 0000 0000 0001  
0010 0000 0000 0010  
0010 0000 0000 0011  
0010 0000 0000 0100  
0010 0000 0000 0101  
0010 0000 0000 0110  
0010 0000 0000 0111  
000 0110 1110  
000 0110 1110  
000 0110 1110  
000 0110 1110  
000 0110 1110  
000 0110 1110  
000 0110 1110  
1
1
1
1
1
1
1
Notes to Tables 3–2 and 3–3:  
(1) The most significant bit (MSB) is on the left.  
(2) The IDCODE’s least significant bit (LSB) is always 1.  
Altera Corporation  
July 2005  
3–3  
Stratix Device Handbook, Volume 1