Configuration
configuration, the device resets registers, enables I/O pins, and begins to
operate as a logic device. The I/O pins are tri-stated during power-up,
and before and during configuration. Together, the configuration and
initialization processes are called command mode. Normal device
operation is called user mode.
SRAM configuration elements allow Stratix devices to be reconfigured in-
circuit by loading new configuration data into the device. With real-time
reconfiguration, the device is forced into command mode with a device
pin. The configuration process loads different configuration data,
reinitializes the device, and resumes user-mode operation. You can
perform in-field upgrades by distributing new configuration files either
within the system or remotely.
PORSELis a dedicated input pin used to select POR delay times of 2 ms
or 100 ms during power-up. When the PORSELpin is connected to
ground, the POR time is 100 ms; when the PORSELpin is connected to
VCC, the POR time is 2 ms.
The nIO_PULLUPpin enables a built-in weak pull-up resistor to pull all
user I/O pins to VCCIO before and during device configuration. If
nIO_PULLUPis connected to VCC during configuration, the weak pull-
ups on all user I/O pins are disabled. If connected to ground, the pull-ups
are enabled during configuration. The nIO_PULLUPpin can be pulled to
1.5, 1.8, 2.5, or 3.3 V for a logic level high.
VCCSELis a dedicated input that is used to choose whether all dedicated
configuration and JTAG input pins can accept 1.5 V/1.8 V or 2.5 V/3.3 V
during configuration. A logic low sets 3.3 V/2.5 V, and a logic high sets
1.8 V/1.5 V. VCCSELaffects the following pins: TDI, TMS, TCK, TRST,
MSEL0, MSEL1, MSEL2, nCONFIG, nCE, DCLK, PLL_ENA, CONF_DONE,
nSTATUS. The VCCSELpin can be pulled to 1.5, 1.8, 2.5, or 3.3 V for a logic
level high.
The VCCSELsignal does not control the dual-purpose configuration pins
such as the DATA[7..0]and PPA pins (nWS, nRS, CS, nCS, and
RDYnBSY). During configuration, these dual-purpose pins will drive out
voltage levels corresponding to the VCCIO supply voltage that powers the
I/O bank containing the pin. After configuration, the dual-purpose pins
use I/O standards specified in the user design.
TDOand nCEOdrive out at the same voltages as the VCCIO supply that
powers the I/O bank containing the pin. Users must select the VCCIO
supply for bank containing TDOaccordingly. For example, when using
the ByteBlaster™ MV cable, the VCCIO for the bank containing TDOmust
be powered up at 3.3 V.
3–6
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005
ALTERA [ ALTERA CORPORATION ]
