IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
Figure 3–1 shows the timing requirements for the JTAG signals.
Figure 3–1. Stratix JTAG Waveforms
TMS
TDI
tJCP
tJCH
t JCL
tJPH
tJPSU
TCK
TDO
tJPXZ
tJPZX
tJPCO
tJSSU
tJSH
Signal
to Be
Captured
tJSCO
tJSZX
tJSXZ
Signal
to Be
Driven
Table 3–4 shows the JTAG timing parameters and values for Stratix
devices.
Table 3–4. Stratix JTAG Timing Parameters & Values
Symbol
tJCP
Parameter
Min Max Unit
100
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCKclock period
tJCH
TCKclock high time
tJCL
50
TCKclock low time
tJPSU
tJPH
JTAG port setup time
20
45
JTAG port hold time
tJPCO
tJPZX
tJPXZ
tJSSU
tJSH
JTAG port clock to output
25
25
25
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
20
45
Capture register hold time
tJSCO
tJSZX
tJSXZ
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
35
35
35
3–4
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005
ALTERA [ ALTERA CORPORATION ]
