Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
Functional Description
1–13
summarizes the concurrent PS configuration modes supported in the
enhanced configuration device.
Table 1–5.
Enhanced Configuration Devices in PS Mode
Mode Name
Passive serial mode
Multi-device passive
serial mode
Multi-device passive
serial mode
Multi-device passive
serial mode
Note to
(1) This is the number of valid
DATA
outputs for each configuration mode.
Mode (n =)
1
2
4
8
Used Outputs
DATA0
DATA[1..0]
DATA[3..0]
DATA[7..0]
Unused Outputs
DATA[7..1]
drive low
DATA[7..2]
drive low
DATA[7..4]
drive low
—
f
For configuration schematics and more information about concurrent configurations,
refer to the appropriate FPGA family chapter in the
External Flash Interface
The enhanced configuration devices support external FPGA or processor access to its
flash memory. The unused portions of the flash memory can be used by the external
device to store code or data. This interface can also be used in systems that implement
remote configuration capabilities. Configuration data within a particular
configuration page can be updated via the external flash interface and the system
could be reconfigured with the new FPGA image. This interface is also useful to store
Nios boot code, application code, or both.
f
For more information about the Stratix remote configuration feature, refer to the
chapter in the
Stratix
Device Handbook.
The address, data, and control ports of the flash memory are internally connected to
the enhanced configuration device controller and to external device pins. An external
source can drive these external device pins to access the flash memory when the flash
interface is available.
This external flash interface is a shared bus interface with the configuration controller
chip. The configuration controller is the primary bus master. Since there is no bus
arbitration support, the external device can only access the flash interface when the
controller has tri-stated its internal interface to the flash. Simultaneous access by the
controller and the external device will cause contention, and result in configuration
and programming failures.
Since the internal flash interface is directly connected to the external flash interface
pins, controller flash access cycles will toggle the external flash interface pins. The
external device must be able to tri-state its flash interface during these operations and
ignore transitions on the flash interface pins.
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