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Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
Functional Description
1
The external flash interface signals cannot be shared between multiple enhanced
configuration devices because this causes contention during in-system programming
and configuration. During these operations, the controller chips inside the enhanced
configuration devices are actively accessing flash memory. Therefore, enhanced
configuration devices do not support shared flash bus interfaces.
The enhanced configuration device controller chip accesses flash memory during:
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FPGA configuration—reading configuration data from flash
JTAG-based flash programming—storing configuration data in flash
At POR—reading option bits from flash
During these operations, the external FPGA or processor must tri-state its interface to
the flash memory. After configuration and programming, the enhanced configuration
device’s controller tri-states the internal interface and goes into an idle mode. To
interrupt a configuration cycle in order to access the flash via the external flash
interface, the external device can hold the FPGA’s nCONFIGinput low. This keeps the
configuration device in reset by holding the nSTATUS-OEline low, allowing external
flash access.
f
For more information about the software support for the external flash interface
feature, refer to the Altera Enhanced Configuration Devices chapter in volume 2 of the
Configuration Handbook. For details about flash commands, timing, memory
organization, and write protection features, refer to the following documents:
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For Micron flash-based EPC4, refer to the Micron Flash Memory MT28F400B3 Data
Sheet at www.micron.com.
For Sharp flash-based EPC16, refer to the Sharp LHF16J06 Data Sheet Flash Memory
Used in EPC16 Devices at www.sharpsma.com.
For the Intel Advanced Boot Block Flash Memory (B3) 28F008/800B3, 28F016/160B3,
28F320B3, 28F640B3 Datasheet, visit www.intel.com.
Configuration Handbook (Complete Two-Volume Set)
© December 2009 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
