1–10
Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
Functional Description
Figure 1–2. FPP Configuration
Enhanced Configuration
Device
V
CC
V
CC (1)
(1)
Stratix Series
or
APEX II Device
WE#C
RP#C
DCLK
WE#F
RP#F
(3)
(3)
n
DCLK
(6)
MSEL
A[20..0]
RY/BY#
CE#
N.C.
N.C.
N.C.
N.C.
N.C.
DATA[7..0]
nSTATUS
CONF_DONE
nCONFIG
DATA[7..0]
(3)
(3)
nCS
OE
nINIT_CONF (2)
OE#
V
(1)
CC
DQ[15..0]
nCE
N.C.
nCEO
V
(7)
WP#
CC
BYTE# (5)
TM1
VCCW
GND
(4)
PORSEL
(4)
PGM[2..0]
(4)
TMO
EXCLK
GND
C-A0 (5)
C-A1 (5)
C-A15 (5)
C-A16 (5)
A0-F
A1-F
A15-F
A16-F
Notes to Figure 1–2:
(1) The VCC should be connected to the same supply voltage as the configuration device.
(2) The nINIT_CONFpin is available on enhanced configuration devices and has an internal pull-up resistor that is always active. This means an
external pull-up resistor is not required on the nINIT_CONF/ nCONFIGline. The nINIT_CONFpin does not need to be connected if its
functionality is not used. If nINIT_CONFis not used, nCONFIGmust be pulled to VCC either directly or through a resistor.
(3) The enhanced configuration devices’ OEand nCSpins have internal programmable pull-up resistors. If internal pull-up resistors are used, external
pull-up resistors should not be used on these pins. The internal pull-up resistors are used by default in the Quartus® II software. To turn off the
internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files.
(4) For PORSEL, PGM[], and EXCLKpin connections, refer to Table 1–10.
(5) In the 100-pin PQFP package, you must externally connect the following pins: C-A0to F-A0, C-A1to F-A1, C-A15to F-A15, C-A16to
F-A16, and BYTE#to VCC. Additionally, you must make the following pin connections in both 100-pin PQFP and 88-pin UFBGA packages:
C-RP#to F-RP#, C-WE#to F-WE#, TM1to VCC, TM0to GND, and WP#to VCC
.
(6) Connect the FPGA MSEL[]input pins to select the FPP configuration mode. For details, refer to the appropriate FPGA family chapter in the
Configuration Handbook.
(7) To protect Intel Flash based EPC devices content, isolate the VCCW supply from VCC. For more information, refer section “Intel-Flash-Based EPC
Device Protection” on page 1–15.
Multiple FPGAs can be configured using a single enhanced configuration device in
FPP mode. In this mode, multiple Stratix series FPGAs, APEX II FPGAs, or both, are
cascaded together in a daisy chain.
After the first FPGA completes configuration, its nCEOpin asserts to activate the nCE
pin for the second FPGA, which prompts the second device to start capturing
configuration data. In this setup, the FPGAs CONF_DONEpins are tied together, and
hence all devices initialize and enter user mode simultaneously. If the enhanced
configuration device or one of the FPGAs detects an error, configuration stops (and
simultaneously restarts) for the whole chain because the nSTATUSpins are tied
together.
1
While Altera FPGAs can be cascaded in a configuration chain, the enhanced
configuration devices cannot be cascaded to configure larger devices or chains.
Configuration Handbook (Complete Two-Volume Set)
© December 2009 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
