1–12
Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
Functional Description
Figure 1–3.
Concurrent Configuration of Multiple FPGAs in PS Mode (n = 8)
V
CC
(1)
V
CC
(1)
Enhanced Configuration
Device
FPGA0
n
(6)
MSEL
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCE
N.C.
nCEO
(3)
(3)
WE#C
RP#C
DCLK
DATA0
DATA1
WE#F
RP#F
A[20..0]
RY/BY#
CE#
OE#
DQ[15..0]
N.C.
N.C.
N.C.
N.C.
N.C.
OE
(3)
nCS
(3)
FPGA1
n
(6)
MSEL
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCE
N.C.
nCEO
GND
nINIT_CONF
(2)
DATA 7
(1)
V
CC
VCCW
WP#
BYTE#
(5)
TM1
PORSEL
PGM[2..0]
EXCLK
V
CC
(7)
GND
(4)
(4)
(4)
FPGA7
n
(6)
MSEL
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCE
N.C.
nCEO
GND
TMO
GND
C-A0
(5)
C-A1
(5)
C-A15
(5)
C-A16
(5)
A0-F
A1-F
A15-F
A16-F
Notes to
(1) Connect V
CC
to the same supply voltage as the configuration device.
(2) The
nINIT_CONF
pin is available on enhanced configuration devices and has an internal pull-up resistor that is always active. This means an
external pull-up resistor is not required on the
nINIT_CONF/nCONFIG
line. The
nINIT_CONF
pin does not need to be connected if its
functionality is not used. If
nINIT_CONF
is not used,
nCONFIG
must be pulled to V
CC
either directly or through a resistor.
(3) The enhanced configuration devices’
OE
and
nCS
pins have internal programmable pull-up resistors. If internal pull-up resistors are used, external
pull-up resistors should not be used on these pins. The internal pull-up resistors are used by default in the Quartus II software. To turn off the
internal pull-up resistors, check the
Disable nCS and OE pull-ups on configuration device
option when generating programming files.
(4) For
PORSEL, PGM[],
and
EXCLK
pin connections, refer to
(5) In the 100-pin PQFP package, you must externally connect the following pins:
C-A0
to
F-A0, C-A1
to
F-A1, C-A15
to
F-A15, C-A16
to
F-A16,
and
BYTE#
to V
CC
. Additionally, you must make the following pin connections in both 100-pin PQFP and 88-pin UFBGA packages:
C-RP#
to
F-RP#, C-WE#
to
F-WE#, TM1
to V
CC
,
TM0
to GND, and
WP#
to V
CC
.
(6) Connect the FPGA
MSEL[]
input pins to select the PS configuration mode. For details, refer to the appropriate FPGA family chapter in the
(7) To protect Intel Flash based EPC devices content, isolate the V
CCW
supply from V
CC
. For more information, refer section
ALTERA [ ALTERA CORPORATION ]
