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EP1C6F256I8 参数 Datasheet PDF下载

EP1C6F256I8图片预览
型号: EP1C6F256I8
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列 [Cyclone FPGA Family]
分类和应用: 可编程逻辑时钟
文件页数/大小: 94 页 / 1066 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Preliminary Information  
Cyclone FPGA Family Data Sheet  
LAB Interconnects  
The LAB local interconnect can drive LEs within the same LAB. The LAB  
local interconnect is driven by column and row interconnects and LE  
outputs within the same LAB. Neighboring LABs, PLLs, and M4K RAM  
blocks from the left and right can also drive an LAB’s local interconnect  
through the direct link connection. The direct link connection feature  
minimizes the use of row and column interconnects, providing higher  
performance and flexibility. Each LE can drive 30 other LEs through fast  
local and direct link interconnects. Figure 3 shows the direct link  
connection.  
Figure 3. Direct Link Connection  
Direct link interconnect from  
left LAB, M4K memory  
block, PLL, or IOE output  
Direct link interconnect from  
right LAB, M4K memory  
block, PLL, or IOE output  
Direct link  
interconnect  
to right  
Direct link  
interconnect  
to left  
Local  
Interconnect  
LAB  
LAB Control Signals  
Each LAB contains dedicated logic for driving control signals to its LEs.  
The control signals include two clocks, two clock enables, two  
asynchronous clears, synchronous clear, asynchronous preset/load,  
synchronous load, and add/subtract control signals. This gives a  
maximum of 10 control signals at a time. Although synchronous load and  
clear signals are generally used when implementing counters, they can  
also be used with other functions.  
Altera Corporation  
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