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EP1C6F256I8 参数 Datasheet PDF下载

EP1C6F256I8图片预览
型号: EP1C6F256I8
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列 [Cyclone FPGA Family]
分类和应用: 可编程逻辑时钟
文件页数/大小: 94 页 / 1066 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Cyclone FPGA Family Data Sheet  
Preliminary Information  
Each LE’s programmable register can be configured for D, T, JK, or SR  
operation. Each register has data, true asynchronous load data, clock,  
clock enable, clear, and asynchronous load/preset inputs. Global signals,  
general-purpose I/O pins, or any internal logic can drive the register’s  
clock and clear control signals. Either general-purpose I/O pins or  
internal logic can drive the clock enable, preset, asynchronous load, and  
asynchronous data. The asynchronous load data input comes from the  
data3input of the LE. For combinatorial functions, the LUT output  
bypasses the register and drives directly to the LE outputs.  
Each LE has three outputs that drive the local, row, and column routing  
resources. The LUT or register output can drive these three outputs  
independently. Two LE outputs drive column or row and direct link  
routing connections and one drives local interconnect resources. This  
allows the LUT to drive one output while the register drives another  
output. This feature, called register packing, improves device utilization  
because the device can use the register and the LUT for unrelated  
functions. Another special packing mode allows the register output to  
feed back into the LUT of the same LE so that the register is packed with  
its own fan-out LUT. This provides another mechanism for improved  
fitting. The LE can also drive out registered and unregistered versions of  
the LUT output.  
LUT Chain & Register Chain  
In addition to the three general routing outputs, the LEs within an LAB  
have LUT chain and register chain outputs. LUT chain connections allow  
LUTs within the same LAB to cascade together for wide input functions.  
Register chain outputs allow registers within the same LAB to cascade  
together. The register chain output allows an LAB to use LUTs for a single  
combinatorial function and the registers to be used for an unrelated shift  
register implementation. These resources speed up connections between  
LABs while saving local interconnect resources. See “MultiTrack  
Interconnect” on page 17 for more information on LUT chain and register  
chain connections.  
10  
Altera Corporation  
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