Preliminary Information
Cyclone FPGA Family Data Sheet
Figure 1. Cyclone EP1C12 Device Block Diagram
IOEs
Logic Array
PLL
EP1C12 Device
M4K Blocks
The number of M4K RAM blocks, PLLs, rows, and columns vary per
device. Table 4 lists the resources available in each Cyclone device.
Table 4. Cyclone Device Resources
Device
M4K RAM
PLLs
LAB Columns LAB Rows
Columns
Blocks
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
1
1
1
2
2
13
17
20
52
64
1
2
2
2
2
24
26
32
48
64
13
17
20
26
32
Altera Corporation
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