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EP1C6F256I8 参数 Datasheet PDF下载

EP1C6F256I8图片预览
型号: EP1C6F256I8
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列 [Cyclone FPGA Family]
分类和应用: 可编程逻辑时钟
文件页数/大小: 94 页 / 1066 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Cyclone FPGA Family Data Sheet  
Preliminary Information  
Cyclone devices contain a two-dimensional row- and column-based  
architecture to implement custom logic. Column and row interconnects of  
varying speeds provide signal interconnects between LABs and  
embedded memory blocks.  
Functional  
Description  
The logic array consists of LABs, with 10 LEs in each LAB. An LE is a small  
unit of logic providing efficient implementation of user logic functions.  
LABs are grouped into rows and columns across the device. Cyclone  
devices range between 2,910 to 20,060 LEs.  
M4K RAM blocks are true dual-port memory blocks with 4K bits of  
memory plus parity (4,608 bits). These blocks provide dedicated true  
dual-port, simple dual-port, or single-port memory up to 36-bits wide at  
up to 200 MHz. These blocks are grouped into columns across the device  
in between certain LABs. Cyclone devices offer between 60 to 288 Kbits of  
embedded RAM.  
Each Cyclone device I/O pin is fed by an I/O element (IOE) located at the  
ends of LAB rows and columns around the periphery of the device. I/O  
pins support various single-ended and differential I/O standards, such as  
the 66-MHz, 32-bit PCI standard and the LVDS I/O standard at up to  
311 Mbps. Each IOE contains a bidirectional I/O buffer and three registers  
for registering input, output, and output-enable signals. Dual-purpose  
DQS, DQ, and DM pins along with delay chains (used to phase-align DDR  
signals) provide interface support with external memory devices such as  
DDR SDRAM, and FCRAM devices at up to 133 MHz (266 Mbps).  
Cyclone devices provide a global clock network and up to two PLLs. The  
global clock network consists of eight global clock lines that drive  
throughout the entire device. The global clock network can provide clocks  
for all resources within the device, such as IOEs, LEs, and memory blocks.  
The global clock lines can also be used for control signals. Cyclone PLLs  
provide general-purpose clocking with clock multiplication and phase  
shifting as well as external outputs for high-speed differential I/O  
support.  
Figure 1 shows a diagram of the Cyclone EP1C12 device.  
4
Altera Corporation  
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