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EP1C6F256I8 参数 Datasheet PDF下载

EP1C6F256I8图片预览
型号: EP1C6F256I8
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列 [Cyclone FPGA Family]
分类和应用: 可编程逻辑时钟
文件页数/大小: 94 页 / 1066 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Preliminary Information  
Cyclone FPGA Family Data Sheet  
The smallest unit of logic in the Cyclone architecture, the LE, is compact  
and provides advanced features with efficient logic utilization. Each LE  
contains a four-input LUT, which is a function generator that can  
implement any function of four variables. In addition, each LE contains a  
programmable register and carry chain with carry select capability. A  
single LE also supports dynamic single bit addition or subtraction mode  
selectable by an LAB-wide control signal. Each LE drives all types of  
interconnects: local, row, column, LUT chain, register chain, and direct  
link interconnects. See Figure 5.  
Logic Elements  
Figure 5. Cyclone LE  
Register chain  
routing from  
previous LE  
LAB-wide  
Synchronous  
Register Bypass  
LAB Carry-In  
Load  
Programmable  
Register  
LAB-wide  
Synchronous  
Clear  
Packed  
Register Select  
Carry-In1  
Carry-In0  
addnsub  
LUT chain  
routing to next LE  
data1  
Row, column,  
and direct link  
routing  
PRN/ALD  
data2  
data3  
Synchronous  
Load and  
Clear Logic  
Look-Up  
Table  
(LUT)  
Carry  
Chain  
D
Q
ADATA  
data4  
ENA  
CLRN  
Row, column,  
and direct link  
routing  
labclr1  
labclr2  
Asynchronous  
Clear/Preset/  
Load Logic  
Local Routing  
labpre/aload  
Chip-Wide  
Reset  
Register chain  
output  
Clock &  
Clock Enable  
Select  
Register  
Feedback  
labclk1  
labclk2  
labclkena1  
labclkena2  
Carry-Out0  
Carry-Out1  
LAB Carry-Out  
Altera Corporation  
9
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