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EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Global Clock Network & Phase-Locked Loops  
does not have dedicated clock output pins. The EP1C6 device in the  
144-pin TQFP package only supports dedicated clock outputs from  
PLL 1.  
Clock Feedback  
Cyclone PLLs have three modes for multiplication and/or phase shifting:  
Zero delay buffer modeThe external clock output pin is phase-  
aligned with the clock input pin for zero delay.  
Normal modeIf the design uses an internal PLL clock output, the  
normal mode compensates for the internal clock delay from the input  
clock pin to the IOE registers. The external clock output pin is phase  
shifted with respect to the clock input pin if connected in this mode.  
You defines which internal clock output from the PLL should be  
phase-aligned to compensate for internal clock delay.  
No compensation modeIn this mode, the PLL will not compensate  
for any clock networks.  
Phase Shifting  
Cyclone PLLs have an advanced clock shift capability that enables  
programmable phase shifts. You can enter a phase shift (in degrees or  
time units) for each PLL clock output port or for all outputs together in  
one shift. You can perform phase shifting in time units with a resolution  
range of 125 to 250 ps. The finest resolution equals one eighth of the VCO  
period. The VCO period is a function of the frequency input and the  
multiplication and division factors. Each clock output counter can choose  
a different phase of the VCO period from up to eight taps. You can use this  
clock output counter along with an initial setting on the post-scale  
counter to achieve a phase-shift range for the entire period of the output  
clock. The phase tap feedback to the m counter can shift all outputs to a  
single phase. The Quartus II software automatically sets the phase taps  
and counter settings according to the phase shift entered.  
Lock Detect Signal  
The lock output indicates that there is a stable clock output signal in  
phase with the reference clock. Without any additional circuitry, the lock  
signal may toggle as the PLL begins tracking the reference clock.  
Therefore, you may need to gate the lock signal for use as a system-  
control signal. For correct operation of the lock circuit below  
–20 C, fIN/N > 200 MHz.  
Altera Corporation  
January 2007  
2–37  
Preliminary  
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