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EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Cyclone Device Handbook, Volume 1  
The Cyclone embedded memory consists of columns of M4K memory  
Embedded  
Memory  
blocks. EP1C3 and EP1C6 devices have one column of M4K blocks, while  
EP1C12 and EP1C20 devices have two columns (see Table 1–1 on  
page 1–2 for total RAM bits per density). Each M4K block can implement  
various types of memory with or without parity, including true dual-port,  
simple dual-port, and single-port RAM, ROM, and FIFO buffers. The  
M4K blocks support the following features:  
4,608 RAM bits  
250 MHz performance  
True dual-port memory  
Simple dual-port memory  
Single-port memory  
Byte enable  
Parity bits  
Shift register  
FIFO buffer  
ROM  
Mixed clock mode  
1
Violating the setup or hold time on the address registers could corrupt the  
memory contents. This applies to both read and write operations.  
Memory Modes  
The M4K memory blocks include input registers that synchronize writes  
and output registers to pipeline designs and improve system  
performance. M4K blocks offer a true dual-port mode to support any  
combination of two-port operations: two reads, two writes, or one read  
and one write at two different clock frequencies. Figure 2–12 shows true  
dual-port memory.  
Figure 2–12. True Dual-Port Memory Configuration  
A
B
dataA[]  
dataB[]  
addressA[]  
wrenA  
addressB[]  
wrenB  
clockA  
clockenA  
qA[]  
clockB  
clockenB  
qB[]  
aclrA  
aclrB  
2–18  
Preliminary  
Altera Corporation  
January 2007  
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