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EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Cyclone Device Handbook, Volume 1  
Figure 2–9. R4 Interconnect Connections  
Adjacent LAB can  
Drive onto Another  
LAB's R4 Interconnect  
R4 Interconnect  
Driving Right  
C4 Column Interconnects (1)  
R4 Interconnect  
Driving Left  
LAB  
Neighbor  
Primary  
LAB (2)  
LAB  
Neighbor  
Notes to Figure 2–9:  
(1) C4 interconnects can drive R4 interconnects.  
(2) This pattern is repeated for every LAB in the LAB row.  
The column interconnect operates similarly to the row interconnect. Each  
column of LABs is served by a dedicated column interconnect, which  
vertically routes signals to and from LABs, M4K memory blocks, and row  
and column IOEs. These column resources include:  
LUT chain interconnects within an LAB  
Register chain interconnects within an LAB  
C4 interconnects traversing a distance of four blocks in an up and  
down direction  
Cyclone devices include an enhanced interconnect structure within LABs  
for routing LE output to LE input connections faster using LUT chain  
connections and register chain connections. The LUT chain connection  
allows the combinatorial output of an LE to directly drive the fast input  
of the LE right below it, bypassing the local interconnect. These resources  
can be used as a high-speed connection for wide fan-in functions from LE  
1 to LE 10 in the same LAB. The register chain connection allows the  
register output of one LE to connect directly to the register input of the  
next LE in the LAB for fast shift registers. The Quartus II Compiler  
automatically takes advantage of these resources to improve utilization  
and performance. Figure 2–10 shows the LUT chain and register chain  
interconnects.  
2–14  
Preliminary  
Altera Corporation  
January 2007  
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