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EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Embedded Memory  
register outputs (number of taps n × width w) must be less than the  
maximum data width of the M4K RAM block (×36). To create larger shift  
registers, multiple memory blocks are cascaded together.  
Data is written into each address location at the falling edge of the clock  
and read from the address at the rising edge of the clock. The shift register  
mode logic automatically controls the positive and negative edge  
clocking to shift the data in one clock cycle. Figure 2–14 shows the M4K  
memory block in the shift register mode.  
Figure 2–14. Shift Register Memory Configuration  
w × m × n Shift Register  
m-Bit Shift Register  
w
w
w
m-Bit Shift Register  
w
n Number  
of Taps  
m-Bit Shift Register  
w
w
w
m-Bit Shift Register  
w
Memory Configuration Sizes  
The memory address depths and output widths can be configured as  
4,096 × 1, 2,048 × 2, 1,024 × 4, 512 × 8 (or 512 × 9 bits), 256 × 16 (or 256 × 18  
bits), and 128 × 32 (or 128 × 36 bits). The 128 × 32- or 36-bit configuration  
Altera Corporation  
January 2007  
2–21  
Preliminary  
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