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EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
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MultiTrack Interconnect  
Figure 2–10. LUT Chain & Register Chain Interconnects  
Local Interconnect  
Routing Among LEs  
in the LAB  
LE 1  
LUT Chain  
Routing to  
Adjacent LE  
Register Chain  
Routing to Adjacent  
LE's Register Input  
LE 2  
LE 3  
LE 4  
LE 5  
LE 6  
LE 7  
LE 8  
LE 9  
Local  
Interconnect  
LE 10  
The C4 interconnects span four LABs or M4K blocks up or down from a  
source LAB. Every LAB has its own set of C4 interconnects to drive either  
up or down. Figure 2–11 shows the C4 interconnect connections from an  
LAB in a column. The C4 interconnects can drive and be driven by all  
types of architecture blocks, including PLLs, M4K memory blocks, and  
column and row IOEs. For LAB interconnection, a primary LAB or its  
LAB neighbor can drive a given C4 interconnect. C4 interconnects can  
drive each other to extend their range as well as drive row interconnects  
for column-to-column connections.  
Altera Corporation  
January 2007  
2–15  
Preliminary  
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