DC and Switching Characteristics
Table 4–7. Arria GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 3 of 3)
-6 Speed Grade
Commercial & Industrial
Description
Condition
Unit
SDI Receiver Jitter Tolerance (8)
JitterFrequency=15KHz
Data Rate = 2.97 Gbps (3G)
REFCLK= 148.5 MHz
> 2
UI
Pattern = Single Line Scramble
Color Bar
No
Equalization
DC Gain = 0 dB
JitterFrequency=100 KHz
Data Rate = 2.97 Gbps (3G)
REFCLK= 148.5 MHz
Pattern = Single Line Scramble
Color Bar
> 0.3
UI
UI
Sinusoidal Jitter Tolerance
(peak-to-peak)
No
Equalization
DC Gain = 0 dB
JitterFrequency=148.5 MHz
Data Rate = 2.97 Gbps (3G)
REFCLK= 148.5 MHz
> 0.3
Pattern = Single Line Scramble
Color Bar
No
Equalization
DC Gain = 0 dB
JitterFrequency=20KHz
Data Rate = 1. 4 85 Gb ps (HD )
REFCLK= 74.25 MHz
P a t t e r n = 7 5 % C o l o r B a r
No Equalization
> 1
UI
UI
DC Gain = 0 dB
Sinusoidal Jitter Tolerance
(peak-to-peak)
JitterFrequency=100KHz
Data Rate = 1. 4 85 Gb ps (HD )
REFCLK= 74.25 MHz
P a t t e r n = 7 5 % C o l o r B a r
No Equalization
> 0.2
DC Gain = 0 dB
Notes to Table 4–7:
(1) Dedicated REFCLKpins were used to drive the input reference clocks.
(2) Jitter numbers specified are valid for the stated conditions only.
(3) Refer to the protocol characterization documents for detailed information.
(4) The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
(5) The jitter numbers for PCI Express are compliant to the PCIe Base Specification 2.0.
(6) The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3.
(7) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(8) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M specifications.
Altera Corporation
May 2008
4–13
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
