Operating Conditions
Tables 4–8 and 4–9 show the transmitter and receiver PCS latency for each
mode, respectively.
Table 4–8. PCS Latency Note (1)
Transmitter PCS Latency
TX
Functional Mode
Configuration
Phase
Comp
FIFO
Byte
TX State
8B/10B
Encoder
TX PIPE
Sum (2)
Serializer Machine
XAUI
-
2-3
3-4
1
1
0.5
-
0.5
1
4-5
6-7
×1, ×4, ×8
8-bit channel
width
1
PIPE
×1, ×4, ×8
16-bit channel
width
1
3-4
1
-
0.5
6-7
GIGE
-
-
2-3
2-3
1
1
-
-
1
4-5
4-5
Serial RapidIO
1.25 Gbps,
2.5 Gbps,
0.5
3.125 Gbps
SDI
HD
10-bit channel
width
-
-
2-3
2-3
1
1
-
-
1
4-5
4-5
HD, 3G
20-bit channel
width
0.5
8-bit/10-bit
channel width
-
-
2-3
2-3
1
1
-
-
1
4-5
4-5
BASIC Single Width
16-bit/20-bit
0.5
channel width
Notes to Tables 4–8:
(1) The latency numbers are with respect to the PLD-transceiver interface clock cycles.
(2) The total latency number is rounded off in the Sum column.
4–14
Altera Corporation
May 2008
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
