DC and Switching Characteristics
Table 4–9. PCS Latency (Part 1 of 2) Note (1)
Receiver PCS Latency
Functional
Mode
Receiver
Phase
Comp
Configuration
Rate
Matcher
(3)
Receiver
State
Byte
De-
Word
Aligner
Deskew
FIFO
8B/10B
Decoder
Byte
Order
Receiver
PIPE
Sum
(2)
Machine serializer
FIFO
XAUI
2-2.5
4-5
2-2.5 5.5-6.5
0.5
1
1
-
1
1
1
1
1-2
2-3
-
14-17
21-25
×1, ×4
8-bit
-
11-13
1
channel
width
PIPE
×1, ×4
16-bit
2-2.5
-
5.5-6.5
0.5
-
1
1
2-3
1
13-16
channel
width
GIGE
Serial
4-5
-
-
11-13
-
1
-
-
1
1
1
1
1-2
1-2
-
-
19-23
6-7
1.25 Gbps, 2-2.5
0.5
RapidIO 2.5 Gbps,
3.125 Gbps
HD
10-bit
channel
width
5
-
-
-
-
1
-
-
1
1
1
1
1-2
1-2
-
-
9-10
6-7
SDI
HD, 3G
2.5
0.5
20-bit
channel
width
Altera Corporation
May 2008
4–15
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
