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EP1AGX50DF780C6 参数 Datasheet PDF下载

EP1AGX50DF780C6图片预览
型号: EP1AGX50DF780C6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 50160 CLBs, 640MHz, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 296 页 / 3505 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Configuration and Testing  
Arria GX devices offer on-chip circuitry for automated checking of single  
event upset (SEU) detection. Some applications that require the device to  
operate error free at high elevations or in close proximity to Earth’s North  
or South Pole will require periodic checks to ensure continued data  
integrity. The error detection cyclic redundancy check (CRC) feature  
controlled by the Device and Pin Options dialog box in the Quartus II  
software uses a 32-bit CRC circuit to ensure data reliability and is one of  
the best options for mitigating SEU.  
Automated  
Single Event  
Upset (SEU)  
Detection  
You can implement the error detection CRC feature with existing circuitry  
in Arria GX devices, eliminating the need for external logic. Arria GX  
devices compute CRC during configuration. The Arria GX device checks  
the computed-CRC against an automatically computed CRC during  
normal operation. The CRC_ERRORpin reports a soft error when  
configuration SRAM data is corrupted, triggering device reconfiguration.  
Custom-Built Circuitry  
Dedicated circuitry is built into Arria GX devices to automatically  
perform error detection. This circuitry constantly checks for errors in the  
configuration SRAM cells while the device is in user mode. You can  
monitor one external pin for the error and use it to trigger a  
reconfiguration cycle. You can select the desired time between checks by  
adjusting a built-in clock divider.  
Software Interface  
Beginning with version 7.1 of the Quartus II software, you can turn on the  
automated error detection CRC feature in the Device and Pin Options  
dialog box. This dialog box allows you to enable the feature and set the  
internal frequency of the CRC between 400 kHz to 50 MHz. This controls  
the rate that the CRC circuitry verifies the internal configuration SRAM  
bits in the Arria GX FPGA.  
f
For more information about CRC, refer to AN 357: Error Detection Using  
CRC in Altera FPGAs.  
This chapter references the following documents:  
Referenced  
Documents  
AN 357: Error Detection Using CRC in Altera FPGAs  
AN414: JRunner Software Driver: An Embedded Solution for PLD JTAG  
Configuration  
AN418: SRunner: An Embedded Solution for Serial Configuration Device  
Programming  
AN423: Configuring the MicroBlaster Passive Serial Software Driver  
3–12  
Altera Corporation  
Arria GX Device Handbook, Volume 1  
May 2008  
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