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EP1AGX50DF780C6 参数 Datasheet PDF下载

EP1AGX50DF780C6图片预览
型号: EP1AGX50DF780C6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 50160 CLBs, 640MHz, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 296 页 / 3505 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Configuration and Testing  
microprocessor and flash memory), AS, and PS configuration schemes.  
Decompression is not supported in the PPA configuration scheme nor in  
JTAG-based configuration.  
Remote System Upgrades  
Shortened design cycles, evolving standards, and system deployments in  
remote locations are difficult challenges faced by system designers.  
Arria GX devices can help effectively deal with these challenges with  
their inherent re programmability and dedicated circuitry to perform  
remote system updates. Remote system updates help deliver feature  
enhancements and bug fixes without costly recalls, reduce time to  
market, and extend product life.  
Arria GX FPGAs feature dedicated remote system upgrade circuitry to  
facilitate remote system updates. Soft logic (Nios® processor or user logic)  
implemented in the Arria GX device can download a new configuration  
image from a remote location, store it in configuration memory, and direct  
the dedicated remote system upgrade circuitry to initiate a  
reconfiguration cycle. The dedicated circuitry performs error detection  
during and after the configuration process, recovers from any error  
condition by reverting back to a safe configuration image, and provides  
error status information. This dedicated remote system upgrade circuitry  
avoids system downtime and is the critical component for successful  
remote system upgrades.  
Remote system configuration is supported in the following Arria GX  
configuration schemes: FPP, AS, PS, and PPA. You can also implement  
remote system configuration in conjunction with Arria GX features such  
as real-time decompression of configuration data for efficient field  
upgrades.  
f
For more information about remote configuration in Arria GX devices,  
refer to the Remote System Upgrades with Arria GX Devices chapter in  
volume 2 of the Arria GX Device Handbook.  
Configuring Arria GX FPGAs with JRunner  
The JRunner software driver configures Altera FPGAs, including  
Arria GX FPGAs, through the ByteBlaster II or ByteBlasterMV cables in  
JTAG mode. The programming input file supported is in Raw Binary File  
(.rbf) format. JRunner also requires a Chain Description File (.cdf)  
generated by the Quartus II software. JRunner is targeted for embedded  
JTAG configuration. The source code is developed for the Windows NT  
operating system (OS), but can be customized to run on other platforms.  
3–8  
Altera Corporation  
Arria GX Device Handbook, Volume 1  
May 2008  
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