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EP1AGX50DF780C6 参数 Datasheet PDF下载

EP1AGX50DF780C6图片预览
型号: EP1AGX50DF780C6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 50160 CLBs, 640MHz, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 296 页 / 3505 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Configuration  
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For more information about the JRunner software driver, refer to the  
AN414: JRunner Software Driver: An Embedded Solution for PLD JTAG  
Configuration and the source files on the Altera web site  
(www.altera.com).  
Programming Serial Configuration Devices with SRunner  
You can program a serial configuration device in-system by an external  
microprocessor using SRunnerTM. SRunner is a software driver  
developed for embedded serial configuration device programming that  
can be easily customized to fit into different embedded systems. SRunner  
reads a raw programming data file (.rpd) and writes to serial  
configuration devices. The serial configuration device programming time  
using SRunner is comparable to the programming time when using the  
Quartus II software.  
f
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For more information about SRunner, refer to the AN418: SRunner: An  
Embedded Solution for Serial Configuration Device Programming and the  
source code on the Altera web site.  
For more information about programming serial configuration devices,  
refer to the Serial Configuration Devices (EPCS1, EPCS4, EPCS64, and  
EPCS128) Data Sheet in the Configuration Handbook.  
Configuring Arria GX FPGAs with the MicroBlaster Driver  
The MicroBlaster™ software driver supports a raw binary file (RBF)  
programming input file and is ideal for embedded FPP or PS  
configuration. The source code is developed for the Windows NT  
operating system, although it can be customized to run on other  
operating systems.  
f
For more information about the MicroBlaster software driver, refer to the  
Configuring the MicroBlaster Fast Passive Parallel Software Driver White  
Paper or the AN423: Configuring the MicroBlaster Passive Serial Software  
Driver on the Altera web site.  
PLL Reconfiguration  
The phase-locked loops (PLLs) in the Arria GX device family support  
reconfiguration of their multiply, divide, VCO-phase selection, and  
bandwidth selection settings without reconfiguring the entire device. You  
can use either serial data from the logic array or regular I/O pins to  
program the PLL’s counter settings in a serial chain. This option provides  
Altera Corporation  
May 2008  
3–9  
Arria GX Device Handbook, Volume 1  
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