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EP1AGX50DF780C6 参数 Datasheet PDF下载

EP1AGX50DF780C6图片预览
型号: EP1AGX50DF780C6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 50160 CLBs, 640MHz, PBGA780, 29 X 29 MM, 1 MM PITCH, FBGA-780]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 296 页 / 3505 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Configuration and Testing  
input buffer. The VCCSEL input pin selects which input buffer is used. The  
3.3-V/2.5-V input buffer is powered by VCCPD, while the 1.8-V/1.5-V  
input buffer is powered by VCCIO  
.
VCCSEL is sampled during power up. Therefore, the VCCSEL setting cannot  
change on-the-fly or during a reconfiguration. The VCCSEL input buffer is  
powered by VCCINT and must be hard-wired to VCCPD or ground. A logic  
high VCCSEL connection selects the 1.8-V/1.5-V input buffer, and a logic  
low selects the 3.3-V/2.5-V input buffer. VCCSEL should be set to comply  
with the logic levels driven out of the configuration device or MAX II  
microprocessor.  
If the design must support configuration input voltages of 3.3 V/2.5 V, set  
VCCSEL to a logic low. You can set the VCCIO voltage of the I/O bank that  
contains the configuration inputs to any supported voltage. If the design  
must support configuration input voltages of 1.8 V/1.5 V, set VCCSEL to a  
logic high and the VCCIO of the bank that contains the configuration  
inputs to 1.8 V/1.5 V.  
f
For more information about multi-volt support, including information  
about using TDOand nCEOin multi-volt systems, refer to the Arria GX  
Architecture chapter in volume 1 of the Arria GX Device Handbook.  
Configuration Schemes  
You can load the configuration data for an Arria GX device with one of  
five configuration schemes (refer to Table 3–4), chosen on the basis of the  
target application. You can use a configuration device, intelligent  
controller, or the JTAG port to configure an Arria GX device. A  
configuration device can automatically configure an Arria GX device at  
system power up.  
You can configure multiple Arria GX devices in any of the five  
configuration schemes by connecting the configuration enable (nCE) and  
configuration enable output (nCEO) pins on each device. Arria GX FPGAs  
offer the following:  
Configuration data decompression to reduce configuration file  
storage  
Remote system upgrades for remotely updating Arria GX designs  
3–6  
Altera Corporation  
Arria GX Device Handbook, Volume 1  
May 2008  
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