Classic EPLD Family Data Sheet
Altera EP910 devices can implement up to 450 usable gates of SSI and MSI
General
Description
logic functions. EP910 devices have 24 macrocells, 12 dedicated input
pins, 24 I/O pins, and 2 global clock pins (see Figure 12). Each macrocell
can access signals from the global bus, which consists of the true and
complement forms of the dedicated inputs and the true and complement
forms of either the output of the macrocell or the I/O input. The CLK1and
CLK2signals are the dedicated clock inputs for the registers in macrocells
13 through 24 and 1 through 12, respectively.
Figure 12. EP910 Block Diagram
Numbers without parentheses are for DIP packages. Numbers in parentheses are for J-lead packages.
2
3
4
1
(3) INPUT
(4) INPUT
(5) INPUT
(2) CLK1
INPUT (43) 39
INPUT (42) 38
INPUT (41) 37
(24) 21
CLK2
5
6
(6)
(7)
(40)
(38)
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
(28)
36
35
34
33
32
31
30
29
28
27
26
25
Macrocell 1
Macrocell 2
Macrocell 3
Macrocell 4
Macrocell 5
Macrocell 6
Macrocell 7
Macrocell 8
Macrocell 9
Macrocell 10
Macrocell 11
Macrocell 12
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
Macrocell 17
Macrocell 18
Macrocell 19
Macrocell 20
Macrocell 21
Macrocell 22
Macrocell 23
Macrocell 24
7
(8)
8
(9)
9
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(18)
Global
Bus
10
11
12
13
14
15
16
17 (19) INPUT
18 (20) INPUT
19 (21) INPUT
INPUT (27) 24
INPUT (26) 23
INPUT (25) 22
768
Altera Corporation
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