Classic EPLD Family Data Sheet
Tables 19 and 20 show the timing parameters for EP910 devices.
Table 19. EP910 External Timing Parameters
Notes (1), (2)
Symbol
Parameter
Conditions EP910-30 EP910-35 EP910-40
Min Max Min Max Min Max
Non-
Turbo
Adder (3)
Unit
tPD1
tPD2
tPZX
tPXZ
tCLR
fMAX
tSU
Input to non-registered output
I/O input to non-registered output
Input to output enable
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF (4)
C1 = 35 pF
(5)
30.0
33.0
30.0
30.0
33.0
35.0
38.0
35.0
35.0
38.0
40.0
43.0
40.0
40.0
43.0
30.0
30.0
30.0
30.0
30.0
0.0
ns
ns
ns
Input to output disable
ns
Asynchronous output clear time
Maximum frequency
ns
41.7
24.0
0.0
37.0
27.0
0.0
32.3
31.0
0.0
MHz
ns
Global clock input setup time
Global clock input hold time
Global clock high time
30.0
0.0
tH
ns
tCH
12.0
12.0
13.0
13.0
15.0
15.0
0.0
ns
tCL
Global clock low time
0.0
ns
tCO1
tCNT
fCNT
Global clock to output delay
C1 = 35 pF
18
21.0
35.0
24.0
40.0
0.0
ns
Global clock minimum clock period (6)
30.0
0.0
ns
Maximum internal global clock
frequency
(6)
33.3
28.6
25.0
0.0
MHz
tASU
tAH
Array clock input setup time
Array clock input hold time
Array clock high time
10.0
15.0
15.0
15.0
10.0
15.0
16.0
16.0
1.0
10.0
15.0
17.0
17.0
1.0
30.0
0.0
0.0
0.0
ns
ns
tACH
tACL
tODH
tACO1
tACNT
fACNT
ns
Array clock low time
ns
Output data hold time after clock
Array clock to output delay
Array clock minimum clock period
C1 = 35 pF (7) 1.0
C1 = 35 pF
ns
33.0
30.0
38.0
35.0
43.0
40.0
30.0
0.0
ns
ns
Maximum internal array clock
frequency
(6)
33.3
28.6
25.0
0.0
MHz
772
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
