Classic EPLD Family Data Sheet
Tables 12 and 13 show the timing parameters for EP610I devices.
Table 12. EP610I External Timing Parameters
Notes (1), (2)
Symbol
Parameter
Conditions EP610I-10 EP610I-12 EP610I-15 Non-Turbo Unit
Adder
Min Max Min Max Min Max
(3)
tPD1
tPD2
tPZX
tPXZ
tCLR
fMAX
Input to non-registered output
I/O input to non-registered output
Input to output enable
C1 = 35 pF
10.0
10.0
15.0
13.0
13.0
12.0
12.0
15.0
15.0
15.0
15.0
15.0
18.0
18.0
18.0
25.0
25.0
25.0
25.0
25.0
0.0
ns
ns
ns
Input to output disable
C1 = 5 pF (4)
ns
Asynchronous output clear time C1 = 35 pF
ns
Maximum frequency
(5)
125.0
100.
0
83.3
MHz
tSU
Global clock input setup time
Global clock input hold time
Global clock high time
7.0
0.0
5.0
5.0
9.0
0.0
5.0
5.0
12.0
0.0
5.0
5.0
25
0.0
0.0
0.0
0.0
25.0
0.0
ns
ns
tH
tCH
tCL
ns
Global clock low time
ns
tCO1
tCNT
fCNT
Global clock to output delay
Global clock minimum period
6.5
8.0
8.0
ns
10.0
12.0
15.0
ns
Maximum internal global clock
frequency
(6)
100.0
83.3
66.0
MHz
tASU
tAH
Array clock input setup time
Array clock input hold time
Array clock high time
1.5
5.5
5.0
5.0
1.0
3.0
6.0
5.0
5.0
1.0
4.0
6.0
6.0
6.0
1.0
25.0
0.0
0.0
0.0
ns
ns
ns
ns
ns
tACH
tACL
tODH
Array clock low time
Output data hold time after clock C1 = 35 pF
(7)
tACO1
tACNT
fACNT
Array clock to output delay
Array clock minimum period
12.0
10.0
14.0
12.0
16.0
15.0
25.0
25.0
0.0
ns
ns
Maximum internal array clock
frequency
(6)
100.0
83.3
66.0
MHz
764
Altera Corporation
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