EP910 EPLD
■
High-performance, 24-macrocell Classic EPLD
Features
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–
–
Combinatorial speeds with tPD as fast as 12 ns
Counter frequencies of up to 76.9 MHz
Pipelined data rates of up to 125 MHz
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■
Programmable I/O architecture with up to 36 inputs or 24 outputs
EP910 and EP910I devices are pin-, function-, and programming file-
compatible
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Programmable clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
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Available in the following packages (see Figure 11)
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–
44-pin plastic J-lead chip carrier (PLCC)
40-pin ceramic and plastic dual in-line packages (CerDIP and
PDIP)
Figure 11. EP910 Package Pin-Out Diagrams
Package outlines are not drawn to scale. Windows in ceramic packages only.
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLK1
INPUT
INPUT
INPUT
I/O
2
3
4
5
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
6
5
4
3
2 1 44 43 42 41 40
7
8
7
39
38
37
36
35
34
33
32
31
30
29
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
9
8
10
11
12
13
14
15
16
17
18
19
20
9
10
11
12
13
14
15
16
17
I/O
I/O
I/O
INPUT
INPUT
INPUT
CLK2
INPUT
INPUT
INPUT
GND
18 19 20 21 22 23 24 25 26 27 28
40-Pin DIP
44-Pin PLCC
EP910
EP910I
EP910
EP910I
Altera Corporation
767
ALTERA [ ALTERA CORPORATION ]
