Classic EPLD Family Data Sheet
Table 11. EP610-25, EP610-30 & EP610-35 Internal Timing Parameters
Unit
Symbol
Parameter
Condition
EP610-25
EP610-30
EP610-35
Min Max Min Max Min Max
tIN
Input pad and buffer delay
I/O input pad and buffer delay
Logic array delay
8.0
2.0
9.0
2.0
11.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIO
tLAD
tOD
tZX
tXZ
tSU
tH
11.0
6.0
14.0
7.0
15.0
9.0
Output buffer and pad delay
Output buffer enable delay
Output buffer disable delay
Register setup time
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
6.0
7.0
9.0
6.0
7.0
9.0
11.0
10.0
11.0
10.0
12.0
10.0
Register hold time
tIC
Array clock delay
13.0
1.0
16.0
1.0
17.0
0.0
tICS
tFD
tCLR
Global clock delay
Feedback delay
3.0
5.0
8.0
Register clear time
13.0
16.0
17.0
Notes to tables:
(1) These values are specified in Table 3 on page 758.
(2) See Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book for information on internal
timing parameters.
(3) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.
(4) Sample-tested only for an output change of 500 mV.
(5) The fMAX values represent the highest frequency for pipelined data.
(6) Measured with a device programmed as a 16-bit counter.
(7) Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter
applies for both global and array clocking.
Altera Corporation
763
ALTERA [ ALTERA CORPORATION ]
