Classic EPLD Family Data Sheet
Tables 8 and 9 show the timing parameters for EP610-15 and EP610-20
devices.
Table 8. EP610-15 & EP610-20 External Timing Parameters
Notes (1), (2)
Symbol
Parameter
Conditions
EP610-15 EP610-20 Non-Turbo Unit
Adder
(3)
Min Max Min Max
tPD1
tPD2
tPZX
tPXZ
tCLR
fMAX
tSU
Input to non-registered output
I/O input to non-registered output
Input to output enable
C1 = 35 pF
15.0
17.0
15.0
15.0
15.0
20.0
22.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
0.0
ns
ns
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF (4)
C1 = 35 pF
(5)
ns
Input to output disable
ns
Asynchronous output clear time
Maximum clock frequency
Global clock input setup time
Global clock input hold time
Global clock high time
ns
83.3
9.0
0.0
6.0
6.0
62.5
11.0
0.0
MHz
ns
20.0
0.0
tH
ns
tCH
8.0
0.0
ns
tCL
Global clock low time
8.0
0.0
ns
tCO1
tCNT
fCNT
Global clock to output delay
Global clock minimum period
11.0
12.0
13.0
16.0
0.0
ns
0.0
ns
Maximum internal global clock
frequency
(6)
83.3
62.5
0.0
MHz
tASU
tAH
Array clock input setup time
Array clock input hold time
Array clock high time
6.0
6.0
7.0
7.0
1.0
8.0
8.0
9.0
9.0
1.0
20.0
0.0
ns
ns
tACH
tACL
tODH
tACO1
tACNT
fACNT
0.0
ns
Array clock low time
0.0
ns
Output data hold time after clock
Array clock to output delay
Array clock minimum period
C1 = 35 pF (7)
1.0
ns
15.0
14.0
20.0
18.0
20.0
0.0
ns
ns
Array clock internal maximum
frequency
(6)
71.4
55.6
0.0
MHz
Table 9. EP610-15 & EP610-20 Internal Timing Parameters (Part 1 of 2)
Symbol
Parameter
Conditions
EP610-15 EP610-20 Unit
Min Max Min Max
tIN
Input pad and buffer delay
I/O input pad and buffer delay
Logic array delay
4.0
2.0
6.0
5.0
5.0
5.0
4.0
2.0
ns
ns
ns
ns
ns
ns
tIO
tLAD
tOD
tZX
tXZ
11.0
5.0
Output buffer and pad delay
Output buffer enable delay
Output buffer disable delay
C1 = 35 pF
C1 = 35 pF
C1 = 5 pF
5.0
5.0
Altera Corporation
761
ALTERA [ ALTERA CORPORATION ]
