Stratix II EP2S60 DSP Development Board Data Sheet
1
Clock Distribution 1 source can be either the oscillator (Y1) or an
external clock inserted using J10. To use an external clock signal,
remove the crystal oscillator from its socket. Make sure to note
the correct orientation of the oscillator before removing it.
The following sections describe the development board components.
Board
Components
Stratix II Device (U18)
The Stratix II EP2S60 device on the board features 24,176 adaptive logic
modules (ALMs) in a speed grade (-4) 1020-pin FineLine BGA® package.
The device has 2,544,192 total RAM bits.
f
For more information on Stratix II devices, refer to the Stratix II Device
Handbook.
Table 6 describes the features of the Stratix II EP2S60F1020C4 device.
Table 6. Stratix II Device Features
Feature
EP2S60F1020
ALMs
24,176
48,352
329
Adaptive look-up tables (ALUTs)
M512 RAM Blocks (32 × 18 bits)
M4K RAM Blocks (128 × 36 bits)
M-RAM Blocks
255
2
Total RAM bits
2,544,192
36
DSP Blocks
Embedded multipliers (based on 18 × 18
mode of operation)
144
Enhanced PLLs
Fast PLLs
4
8
Maximum user I/O pins
Package type
Board reference
Voltage
717
1020-pin FineLine BGA
U18
1.2 V (internal), 3.3 V (I/O)
16
Altera Corporation
Preliminary
ALTERA [ ALTERA CORPORATION ]
