Stratix II EP2S60 DSP Development Board Data Sheet
Table 4. Clock Distribution Signals (Part 3 of 3)
Signal Name
Comes From
Goes To
proto1_CLKOUT,
proto2_CLKOUT
PROTO1 (J25 pin 13)
PROTO2 (J28 pin 13) via T30
a buffer (U7)
Stratix II device pins T32 and
Notes to Table 4:
(1) J3 and J4 control which clock is routed to the A/D converters. See Table 10 for
details.
(2) J18 and J19 control which clock is routed to the D/A converters. See Table 16 for
details.
The Stratix II EP2S60 DSP development board can obtain a clock source
from one or more of the following sources:
■
■
The on-board crystal oscillator
An external clock (through an SMA connector or a Stratix II pin)
The board can provide independent clocks from both the enhanced and
fast PLLs to the A/D converters, the D/A converters, and the other
components that require stable clock sources.
To implement this concept, the enhanced PLL5-dedicated pins drive the
A/D converters and associated functions, and the enhanced
PLL6-dedicated pins drive the D/A converters and associated functions.
14
Altera Corporation
Preliminary
ALTERA [ ALTERA CORPORATION ]
