Non-Volatile Configuration
Table 4. Clock Distribution Signals (Part 2 of 3)
Signal Name
Comes From
Goes To
dac_PLLCLK2_n
Stratix II device pin D16 DAC B (U15 pin 28) (2)
(PLL5_OUT1n)
sdram_CLK
adc_PLLCLK1
adc_PLLCLK2
audio_CLK
Stratix II device pin AK16 SDRAM (U39 U40 pins 68)
(PLL6_OUT0p)
Stratix II device pin B18
(PLL11_OUT0p)
ADC A (U1 pins 8, 7) (1)
ADC B (U2 pins 8, 7) (1)
Audio CODEC (U5 pin 25)
Stratix II device pin
D18(PLL11_OUT0n)
Stratix II device pin
AL18(PLL12_OUT0p)
pld_MICTORCLK
pld_CLKOUT
Stratix II device pin M25 Mictor Connector (J20 pin 5)
Stratix II device pin J14
PROTO1 (J25 pin 11) and
PROTO2 (J28 pin 11) via a
buffer (U7)
pld_CLKIN0,pld_CLK 100-MHz oscillator
IN1
Stratix II device pins AM17
and A16
pld_CLKIN0_n,pld_C External CLKIN_n input
Stratix II device pins AL17
and B16
LKIN1_n
(J11)
proto1_OSC,
proto2_OSC
100-MHz oscillator
PROTO1 (J25 pin 9) and
PROTO2 (J28 pin 9) via a
buffer (U7)
cpld_CLKOSC
100-MHz oscillator
100-MHz oscillator
CPLD (U10 pin 125)
adc_CLK_IN1,
adc_CLK_IN2
ADC A (U1 pins 8, 7) and B
(U2 pins 8, 7) (1)
dac_CLKIN1,
dac_CLKIN2
100-MHz oscillator
DAC A (U14 pin 28) and B
(U15 pin 28) (2)
pld_CLKFB
pld_CLKOUT signal from Stratix II device pin U1
the Stratix II pin J14
adc_CLK_IN1_n,
adc_CLK_IN2_n
External CLKIN_n input
(J11)
ADC A (U1 pins 8, 7) and B
(U2 pins 8, 7) (1)
dac_DACCLKIN1,
dac_DACCLKIN2
External DA_EXT_CLK
input (J12)
DAC A (U14 pin 28) and B
(U15 pin 28) (2)
pld_DACCLKIN
External DA_EXT_CLK
input (J12)
Stratix II device pin E16
Altera Corporation
13
Preliminary
ALTERA [ ALTERA CORPORATION ]
