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DPCLK0 参数 Datasheet PDF下载

DPCLK0图片预览
型号: DPCLK0
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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5–6  
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family  
Clock Networks  
GCLK Network Clock Source Generation  
Figure 5–2 shows Cyclone III device family PLLs, clock inputs, and clock control  
block location for different device densities.  
(1)  
Figure 5–2. PLL, CLK[], DPCLK[], and Clock Control Block Locations in the Cyclone III Device Family  
DPCLK[11.10]  
DPCLK[9..8]  
CDPCLK7  
CDPCLK6  
CLK[11..8]  
2
2
4
4
(3)  
PLL  
2
PLL  
3
4
5
CDPCLK0  
CDPCLK5  
(3)  
(2)  
(2)  
2
4
4
Clock Control  
Block (1)  
5
2
GCLK[19..0]  
20  
DPCLK0  
DPCLK7  
CLK[7..4]  
DPCLK6  
20  
20  
CLK[3..0]  
DPCLK1  
4
4
20  
GCLK[19..0]  
Clock Control  
Block (1)  
2
4
4
5
2
4
(2)  
(2)  
(3)  
CDPCLK4  
CDPCLK1  
5
PLL  
4
PLL  
1
(3)  
4
4
2
2
CDPCLK3  
CDPCLK2  
CLK[15..12]  
DPCLK[3..2]  
DPCLK[5..4]  
Notes to Figure 5–2:  
(1) There are five clock control blocks on each side.  
(2) Only one of the corner CDPCLKpins in each corner can feed the clock control block at a time. You can use the other CDPCLKpins as  
general-purpose I/O pins.  
(3) Remote clock pins can feed PLLs over dedicated clock paths. However, these paths are not fully compensated.  
Cyclone III Device Handbook  
Volume 1  
July 2012 Altera Corporation  
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