DPCLK0 参数 Datasheet PDF下载

型号：	DPCLK0
PDF下载：	下载PDF文件查看货源
内容描述：	的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用：
文件页数/大小：	274 页 / 7302 K
品牌：	ALTERA [ ALTERA CORPORATION ]

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

5–3

Clock Networks

Table 5–1. Cyclone III Device Family GCLK Network Connections (Part 2 of 2)

(1)

GCLK Networks

GCLK Network Clock

Sources

10 11 12 13 14 15 16 17 18 19

PLL4_C1

PLL4_C2

PLL4_C3

PLL4_C4

DPCLK0

DPCLK1

DPCLK7

—

(4)

CDPCLK0, or

—

(2), (5)

CDPCLK7

DPCLK2

(4)

CDPCLK1, or

—

(2), (5)

CDPCLK2

DPCLK5

DPCLK7

DPCLK4

DPCLK6

(4)

(2)

(4)

(2)

(4)

—

CDPCLK5, or

—

(2), (5)

CDPCLK6

DPCLK3

(4)

CDPCLK4, or

—

(2), (5)

CDPCLK3

DPCLK8

—

DPCLK11

DPCLK9

DPCLK10

DPCLK5

DPCLK2

DPCLK4

DPCLK3

Notes to Table 5–1:

(1) EP3C5 and EP3C10 devices only have GCLK networks 0 to 9.

(2) These pins apply to all devices in the Cyclone III device family except EP3C5 and EP3C10 devices.

(3) EP3C5 and EP3C10 devices only have phase-locked loops (PLLs) 1 and 2.

(4) This pin applies only to EP3C5 and EP3C10 devices.

(5) Only one of the two CDPCLKpins can feed the clock control block. You can use the other pin as a regular I/O pin.

July 2012 Altera Corporation

Cyclone III Device Handbook

Volume 1

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