欢迎访问ic37.com |
会员登录 免费注册
发布采购

DPCLK0 参数 Datasheet PDF下载

DPCLK0图片预览
型号: DPCLK0
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号DPCLK0的Datasheet PDF文件第63页浏览型号DPCLK0的Datasheet PDF文件第64页浏览型号DPCLK0的Datasheet PDF文件第65页浏览型号DPCLK0的Datasheet PDF文件第66页浏览型号DPCLK0的Datasheet PDF文件第68页浏览型号DPCLK0的Datasheet PDF文件第69页浏览型号DPCLK0的Datasheet PDF文件第70页浏览型号DPCLK0的Datasheet PDF文件第71页  
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family  
5–7  
Clock Networks  
The inputs to the five clock control blocks on each side must be chosen from among  
the following clock sources:  
Four clock input pins  
Five PLL counter outputs  
Two DPCLKpins and two CDPCLKpins from both the left and right sides, and four  
DPCLKpins and two CDPCLKpins from both the top and bottom  
Five signals from internal logic  
From the clock sources listed above, only two clock input pins, two PLL clock outputs,  
one DPCLKor CDPCLKpin, and one source from internal logic can drive into any given  
clock control block, as shown in Figure 5–1 on page 5–5.  
Out of these five inputs to any clock control block, the two clock input pins and two  
PLL outputs are dynamically selected to feed a GCLK. The clock control block  
supports static selection of the signal from internal logic.  
Figure 5–3 shows a simplified version of the five clock control blocks on each side of  
the Cyclone III device family periphery.  
(1)  
Figure 5–3. Clock Control Blocks on Each Side of the Cyclone III Device Family  
4
Clock Input Pins  
5
PLL Outputs  
Clock  
Control  
Block  
2
5
CDPCLK  
GCLK  
2 or 4  
DPCLK  
5
Internal Logic  
Five Clock Control  
Blocks on Each Side  
of the Device  
Note to Figure 5–3:  
(1) The left and right sides of the device have two DPCLKpins; the top and bottom of the device have four DPCLKpins.  
GCLK Network Power Down  
You can disable the Cyclone III device family GCLK (power down) by using both  
static and dynamic approaches. In the static approach, configuration bits are set in the  
configuration file generated by the Quartus II software, which automatically disables  
unused GCLKs. The dynamic clock enable or disable feature allows internal logic to  
control clock enable or disable of the GCLKs in the Cyclone III device family.  
When a clock network is disabled, all the logic fed by the clock network is in an  
off-state, thereby reducing the overall power consumption of the device. This function  
is independent of the PLL and is applied directly on the clock network, as shown in  
Figure 5–1 on page 5–5.  
You can set the input clock sources and the clkenasignals for the GCLK multiplexers  
through the Quartus II software using the ALTCLKCTRL megafunction.  
f
For more information, refer to the Clock Control Block (ALTCLKCTRL) Megafunction  
User Guide.  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 1  
 复制成功!